Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The CLBs, IOBs, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
In a PLD, as in other integrated circuits (ICs), the various CLBs, IOBs, and interconnect are formed on a single substrate. FIG. 1A shows a first silicon substrate on which NMOS 101 and PMOS 102 transistors are formed. The silicon substrate 100 is positively doped (P-type). Therefore, to form a PMOS transistor, an “IN-well” (negatively doped region) 112 is diffused into substrate 100, and the PMOS transistor 102 is formed within N-well 112.
FIG. 1B shows a second silicon substrate for a CMOS integrated circuit (IC) formed using a “triple-well” process. When the triple-well process is used, NMOS transistors 101 are formed within “P-wells” (positively doped regions) 111, within larger N-wells 113, which in turn reside within P-type substrate 100. Similarly, all PMOS transistors 102 are formed within N-wells 112, which also reside within P-type substrate 100. Thus, the P-wells 111 and N-wells 112 are electrically isolated, both from each other and from all other wells in the substrate.
FIG. 1C shows a third silicon substrate formed using an “SOI”, or silicon-on-insulator, process. When an SOI process is used, NMOS transistors 101 are formed within P-wells 111, and PMOS transistors 102 are formed within N-wells 112. Each of P-wells 111 and N-wells 112 reside within an electrically insulating substrate 110. Thus, the substrate insolates the P-wells and N-wells from each other and from all other wells in the substrate.
Over time, IC designers are reducing the “VCC” or power high voltage level at which ICs are designed to operate. This reduction in VCC has the advantage of reducing power consumption in an IC. However, it also has the undesirable effect of reducing performance in the IC. Therefore, it is desirable to find ways to counteract this decrease in performance. One method is to apply a voltage bias to the wells in which the transistors reside.
When either a triple-well or an SOI process is used, the P-wells and N-wells can be biased to voltage levels different from each other and from other wells of the same type. An applied voltage differential is referred to as a “substrate bias” or (when applied to a well) a “well bias”.
FIGS. 1B and 1C shows examples of the application of well biasing to P-wells and N-wells. For example, for an NMOS transistor 101, a positive well bias 105 of about 0.4 to 0.6 volts can be applied to P-well 111. In other words, if P-well 111 is normally at ground (0 volts), the P-well is driven to about 0.4 to 0.6 volts.
Similarly, for a PMOS transistor 102 a positive well bias 106 of about −0.4 to −0.6 volts can be applied to an N-well 112. In other words, the so-called “positive well bias” drives the N-well to a negative voltage relative to the original voltage level. For example, for a PMOS transistor 102, if the N-well is normally at VCC (power high), the N-well is driven to about VCC−0.4 to VCC−0.6 volts.
As the term is used herein, applying a more positive voltage to a P-well or a more negative voltage to an N-well is called applying a “positive well bias”. Thus, applying a positive well bias effectively reduces the reverse well bias of the transistors within the well. Also as used herein, applying a more negative voltage to a P-well or a more positive voltage to an N-well is called applying a “negative well bias”. Thus, applying a negative well bias effectively increases the reverse well bias of the transistors within the well.
By changing the voltage level of a well, the threshold voltage (Vt) of the transistors within the well is altered. For example, an increased positive voltage in a P-well (i.e., a positive well bias) causes a drop in the threshold voltage of the NMOS transistors within the well. This lower threshold voltage, in turn, increases the saturation drain current, which increases the performance of all of the NMOS transistors within the biased well.
The reverse situation is also true. For example, a lower voltage in a P-well (i.e., a negative well bias) causes a rise in the threshold voltage of the NMOS transistors within the well, resulting in a reduced leakage current. Gitlin et al. describe one example of using a negative well bias to reduce leakage current in U.S. Pat. No. 5,880,620, entitled “Pass Gate Circuit with Body Bias Control”, which is hereby incorporated by reference. However, the application of a negative well bias also has the effect of reducing the performance of the transistor.
While the application of a positive well bias increases the performance of a transistor, the faster operation has its price. Besides increasing the saturation drain current, the positive well bias also increases the amount of current flowing through an inactive transistor. This current is a major component of leakage current in a CMOS integrated circuit (IC). Therefore, applying a positive well bias to all the transistors on an IC certainly improves the performance of the device, but can also lead to an unacceptably large leakage current.
To address this limitation, “fixed function” logic devices (as opposed to programmable logic devices, or PLDs) can be designed with positive well bias applied only to circuits that are particularly speed-critical. By applying this technique, the speed advantage is gained only where necessary, while the increase in leakage current is kept within acceptable bounds.
However, the problem of increased leakage current with an applied positive well bias is not so easily addressed in PLDS. In PLDs, the critical circuits and paths are not limited to specific areas of the device or to specific transistors. For example, in an FPGA, a user can program any of the CLBs to perform a speed-critical function, and a path between two such CLBs can traverse any of a large number of interconnect paths. Therefore, in the past, to take advantage of positive well biasing in a PLD would have required the well biasing of each transistor in the programmable areas of the device, to ensure that the critical paths used the biased transistors. As PLDs increase in size, to the point where many millions of transistors are used in each PLD, leakage currents are becoming a limiting factor in many designs. Therefore, it has not been possible to take advantage of positive well biasing in the design of large PLDs.
It is therefore desirable to provide structures and methods enabling the application of well biasing techniques to large PLDS.